The FPGA Implementation And Optimization Of Secure Hash Algorithm SHA-3

SHA-3 algorithm is the latest secure hash algorithm,which is widely used in the field of communication security,undertakes the tasks of calculating message digests and ensuring information integrity in the current and future years.This paper implements the SHA-3 algorithm on the FPGA based on the principle of the SHA-3 algorithm,jobs include:(1)This paper conduct an evaluation on the major architectures and optimization methods in the FPGA implementation of the SHA-3 algorithm,including basic hardware implementation without pipeline and loop folding,high-throughput hardware implementation using sub-pipeline,loop unrolling and pipeline,compact hardware implementation using lane-wise and slice-wise loop folding,the implementation scheme using various architectures and optimization methods in this paper achieves the best performance compared with other literatures.(2)In the basic and high-throughput hardware implementation,we implement the data sharing operation of the algorithm steps in LUT6₂,one LUT6₂ gets 2-bit data output,finally in the basic hardware,the number of LUTs has been reduced by 30%and resource utilization has been increased by 11%,and the high-throughput hardware implementation scheme combined with loop unrolling and pipeline technology has reached a maximum throughput of 18.912 Gbps and a resource utilization of 12.80 Mbps/Slice.(3)For the lane-wise loop folding scheme in the compact hardware implementation,we use control logic in the form of instructions,use distributed RAM to store the state,use the address conversion module to complete the address conversion within 1 clock,and use LUT6₂ to merge logical units of different steps,the implementation scheme uses 260 slices and 2402 clocks to complete the SHA-3 calculation,reaching a throughput of 164 Mbps.(4)For the slice-wise loop folding scheme in the compact hardware implementation,we use SRL to store the state,complete the p and ? steps of the algorithm during the SRL reading process,and solve the data coverage problem of p step by alternately storing between the two SRL,this paper implements two slice-wise folding schemes.The scheme with fewer delay clocks uses 1689 clocks to achieve 144 Mbps throughput,and the scheme with smaller area uses 106 slices to achieve 1.18 Mbps/Slice resource utilization.