Design And Implementation Of A Scalable Pipeline FFT Processor Based On FPGA

With the rapid development of electronic and integrated circuit technology, digital signal processing has been widely applied in various fields, such like communication systems, signal processing, biomedical engineering, autocontrol engineering and so on. Discrete Fourier transform (DFT) and its fast algorithms as a basic transform in digital signal processing also have been widely used. In recent years, FFT based OFDM technology has arisen and has been used in many communication systems, and this fact pushes the investigation on FFT processor to a new level.It's has been more than forty years since FFT algorithm firstly presented, the theory of FFT algorithm is much mature today ,but the method of how to implement it is still worth discussing. The real-time compution of FFT with high-speed and large capacity of data flow can be realized by parallel data processing or multilevel pipeline processing. It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.In this paper, after analyzing and comparing all kinds of FFT algorithms, the mixed radix 2 and radix 4 decimation in frequency FFT algorithm is chosen to realize the FFT processor, also a high speed and scalable pipeline architecture is proposed. Using the chosen FFT algorithm and pipeline architecture, a FFT processor is designed and implemented, it has already been applied in a DAB receiver successfully. The RTL level simulation result of the FFT processor shows that the processor has the same output as the FFT model in C language. The FFT processor also be tested under FPGA environment, the waveform simulation also shows the processor performs a correct function. When synthesized by QuartusⅡ,its highest working frequency reaches 133 MHz, that means the high processing goal is obtained.