The Research And Design Of Cryptographic Chip Based On SMS4Algorithm

With the rapid development and wide application space of Wireless Local Area Network, ensuring its safety becomes more and more important. The core technology of information security is cryptography, so the research of it becomes rather important.SMS4algorithm is the first commercial cipher algorithm, which is released by the state cryptography administration office. It is very important and has a better ability to resist crack.This project researches the hardware implementation of SMS4algorithm. Respectively, it introduces several main way of hardware implementation in the paper, including the loop iteration, the full pipelining, the combination with2stages pipelining and loop, the combination with4stages pipelining and loop, the combination with8stages pipelining and loop, and the combination with16stages pipelining and loop. The loop iteration has area optimization at the expense of speed. The full pipelining improves the performance at the expense of area. The combination with2stages pipelining and loop and the combination with4stages pipelining and loop have the priority of area. The combination with16stages pipelining and loop has the priority of speed. The combination with8stages pipelining and loop is balanced on area and speed. Every way has its applicable environment, and has its respective advantages and disadvantages.The main job of this project includes three parts. First, we need to design the structure of different implementations respectively, define the functional modules and interface signal. Secondly, build the RTL model and do the simulation of different methods with ModelSim. Finally, do the synthesis optimization, place and route, timing simulation with Quartus II, and do the verification by FPGA. At the same time we can view the result of area, clock frequency and power consumption with Quartus Ⅱ.Finally, we can get the following results. First, the total logic elements of the loop iteration are5063, and the speed of finishing one grouped data is509.952ns. Second, the total logic elements of the full pipelining are34673, and the speed of finishing one grouped data is9.976ns. Third, the total logic elements of the combination with4 stages pipelining and loop are10289, and the speed of finishing one grouped data is57.256ns.