A Segmented Output Stage H-Bridge IC with Tunable Gate Driver

In this thesis, an integrated H-bridge is presented for continuously optimizing the power conversion efficiency over a wide range of output current. The proposed IC incorporates both segmented output transistors and segmented gate drivers. This fully segmentation approach allows to flexibly change the on-resistance of the output stage power transistors and the output resistance of the gate drivers. Dynamic adjustment of these parameters allows to investigate the best combination of output power transistor size and gate driver size for any given load current. The IC chip is fabricated using TSMC's 0.18 mum BCD Gen-2 process technology. The presented design when operating as a buck converter with a load current between 0.02 A and 4 A achieves efficiency improvements of 32% and 8% at light and heavy load current, respectively. Furthermore, the dynamically adjustable gate driver output resistance allows for suppression of the peak CEMI by 5.5 dBm.