Research And Optimization Of Di/dt Controllability Of U-Shaped Channel SOI-LIGBT

Silicon on Insulator Lateral Insulated Gate Bipolar Transistor(SOI-LIGBT)is the core switching device in single-chip intelligent power chips because of its high input impedance,high current density and easy integration.The U-shaped channel SOI-LIGBT device has the advantage of high current density,which helps to reduce the chip area and cost.However,due to the unique channel structure,the di/dt of the U-shaped channel device is too high and uncontrolled,resulting in problems such as high turn-on loss,high noise,and high latch-up risk.Therefore,research and optimization of the di/dt controllability of the U-shaped channel SOI-LIGBT device are of great significance.The study found that during the second turn-on process of the double-pulse test,due to the rapid accumulation of hole carriers in the JFET region of the U-shaped channel SOI-LIGBT device,the voltage at this location rapidly rises and a negative gate capacitance phenomenon occurs.The displacement current formed by the negative gate capacitance can easily cause the gate voltage overshoot of the device,which reduces the controllability of the di/dt of the device.Based on the theoretical analysis,a segmented gate structure is proposed in this paper,which divides the original gate into the first gate and the second gate.Except for the gate part,the segmented gate structure does not change the other parts of the U-shaped channel SOI-LIGBT device,and does not add additional masks and process steps.The first and second gates of the segmented gate structure are connected to external signals by different resistances,and the resistance value of the first gate resistance is much larger than that of the second gate resistance.During the opening process,the rate voltage rise of the second gate is greater than that of the JFET region below it,thus avoiding the overshoot of the gate voltage.The design scheme improves the di/dt controllability of the U-shaped channel device without affecting the current and voltage capabilities of the device.The simulation results shows that under the condition of E_ON=41.8?J,the di/dt of the device drops by about74%.Under the bus voltage of 280V,the load current of 0.5A,the first gate resistance of 800?and the second gate resistance of 5?,the di/dt is reduced from 86.2A/?s to 41.9A/?s,and the turn-on loss is reduced from 49.5?J to 39.8?J.The design targets are reached.