Design Of 10bit 160MSPS Segmented Current Steering DAC

Digital to analog converter is a core module in wireless communication system,which is used to receive digital signals and complete the conversion from digital signals to analog signals.Therefore,the research of DAC has been widely concerned.It is of great significance to develop a DAC with high performance,low power consumption and low area.Under this background,this project is based on SMIC 55nm technology,with the design of segmented current steering DAC as the core,and the main research achievements are as follows:1.Based on the segmented current steering DAC circuit structure,a digital to analog converter chip was developed.Its resolution is 10bit and sampling rate is160MSPS.2.Based on Cadence Virtuoso software platform,the circuit structure of 10bit160MSPS DAC is built.In the internal module circuit,a reference current source with output current temperature coefficient of 3.1ppm/?is designed to replace the bandgap reference voltage source in the traditional circuit structure;the circuit simulation environment is established by using ADE simulation tool,and the whole DAC circuit is simulated under different temperature and input signal conditions.The simulation results show that the DAC can work normally in the temperature range of-40?to120?;when the sampling frequency is 160MHz,the received signal frequency range is 0 to 80MHz.3.A layout design method of high and middle current source cross layout is proposed.Compared with the traditional Q~2 random walk current source layout method,this layout method is simpler and optimizes the routing complexity.The results show that the current source layout method proposed in this paper can reduce the random error caused by layout mismatch.Finally,the post simulation results show that the DAC is effective SFDR=78d B@fin=40MHz.The total area of the layout including dual signal channels is 0.84mm~2,and the total power consumption is 31m W.