Study Of Digital SOC Test Technology Based On Embedded Core Test Reuse

SOC(System-On-a-Chip) is widely used, which is attribute to the rapid development of deep submicron manufacture technology and design technology of integrated circuit. As system design scale is more and more complex, SOC test becomes more and more difficult than ever because different multi IP cores will be integrated into a system. The strategy of embedded core test reuse could solve this problem. So the study of test system for SOC embedded cores test reuse is of the great importance in the theory research and the practical application.Based on studying IEEE P1500 standard in detail, this paper presents a test system which includes hardware proportion and software proportion for embedded core test reuse. The hardware proportion includes a test controller which will generate signals needed by the IEEE P1500 standard and an interface circuit. The software proportion includes the test vectors generation module, text compilation module, hardware driven module, and faults diagnosis module. Meanwhile, The test metrology defined by the IEEE P1500 standard is discussed, and what's more, a practical experiment on the DEMO circuit has been done.Simulation and practical test results show that the metrology is feasible. The performance of the test system meets with requirements of SOC test. The test system illustrated in the dissertation has a prospective future in the applications.