Design Of FFT IP Core And Research Of Design For Test

With the development of integrated circuit technology, the integration and complexity of circuit were more and more increasingly. A series of issues such as testing were brought. DFT was one method that testing and designing of circuit were considered at the same time. DFT has already become an important part of the IC design. Radix-2FFT was the base algorithm of this IP core design. Sequential processing structure was adopted as the architecture of this IP core. The entire FFT IP core was divided into several modules according to Top-down design method, and each module was programmed by using VHDL. Synthesys and simulations were accomplished under QuartusII software environment. The accuracy of the design has been confirmed by comparing between the simulation results of the designed IP core and the theoretical results of Matlab. In this design, the 8-bit ripple carry adder was designed as an example when describing the principle of BIST. The efficiency and speed of testing can be showed by the results of this design.