| High-performance circuit design in gigahertz clock frequency requires extensive use of dynamic logic. Prevalent application of dynamic logic provides high speed but can entail serious problems in digital circuit design. Such problems are intrinsic logic synthesis problems associated with monotonic property, high power consumption in dynamic or standby mode, and signal integrity in deep submicron technology.; In this thesis, we first address domino logic synthesis issues. Domino logic is intrinsically monotonic and thus cannot implement inverting logic. To overcome such a structural limitation, a small static CMOS logic is used in the circuit to avoid significant area penalty due to logic duplication in the prior art. To minimize the static CMOS logic part, a generalized ATPG-based logic transformation is proposed to eliminate or relocate trapped inverters.; Capacitive coupling between adjacent nets affects both the functionality and the timing response of a circuit. When incident charge shift due to crosstalk is beyond the noise margin of a cell, the output logic value of the cell can be changed erroneously. To address this problem, a new concept of crosstalk immunity set is introduced and applied to minimize the crosstalk in domino logic circuit.; The design of microelectronic systems with low power consumption has become important recently. As chips continue to become larger yet denser, energy-efficient design considerations such as reliability, portability, and thermal management have become critical concerns. For interconnects, we characterize the cycle-averaged power in terms of switching statistics and dynamic behaviors. The interconnect design is then engineered to minimize the power consumption while meeting routing and crosstalk constraints.; Increased coupling capacitance can also significantly change timing characteristics of a circuit. When two adjacent wires have the same polarity signal transitions, the latch at the receiving end may fail due to the hold time violation, namely, the min-delay constraint. On the other hand, the opposite polarity transitions on adjacent wires can lead to the setup time violation, namely, the max-delay constraint. We propose an algorithm for minimizing circuit delay through timing window modulation in dual threshold voltage technology.; Since intermodule buses and interconnects are significant sources of power consumption, novel low-power bus-encoding schemes are proposed in this thesis to minimize the coupled switchings that dominate the on-chip bus power consumption. |
