Research On Reconfigurable Dynamic Logic Computing

Nowadays, mainstream of the architecture of the international high performance computing is based on the computer theory of Von Neumann. However, the architecture of Von Neumann is confronted with many insurmountable obstacles of development:in the aspect of availability, the real application performance of the existing architecture could only achieve the 5%-10% of the peak value; in the aspect of application, due to the single fixed configuration, the users could not join the control between configurations of computing resources and computing processes. Particularly, in the designing of processor chips based on silicon, the chips could only be locked into special functions such that the existing CPU lacks controllability, flexibility and variability. So, the basic scientific research of constructing logic gate circuit and chips with dynamic reconfigurable abilities become the front and hotspot of the existing international researches.Traditionally, the field programmable gate array (FPGA) is used to realize different functions through the breaking of circuit connections. But FPGA is relatively slow due to its reconfigure tasks, typically by taking milliseconds for each rewiring, which is million times slower than chips of dynamic logic architecture in changes. Such characteristic of FPGA largely influenced its application. Due to the limitation of transformation speed, in practical applications, FPGA is usually used to the designing of special chips. So for the past decades, the idea of a novel commuting principle, i.e. chaos computing was put forward to breakthrough the rewiring limitation of FPGA and made the reconfigurable computing more flexible.Chaos computing, proposed by Sinha and Ditto in 1998, was selected as the top physics stories for 1998 by American Institute of Physics and was widely reported by Science News, Science Daily, Scientific American and Technology Review published by MIT. Extreme tech regarded Chaos Computing as "The 10 Coolest Technologies You've Never Heard Of".Under the circumstances of not varying the circuit structure, the chaos computing uses fixed circuit structure and internal dynamical characteristics of chaotic systems to ensure that the logic element could transform between different logical functions by applying small changes to the system parameters. Compared to the existing FPGA techniques, chaos computing which realizes by harnessing dynamics theoretically possesses better flexibility and has stronger functions. In 2008, a prototype VLSI chip (TSMC CMOS,30Mhz clock) was designed and developed, and which can change the functions and type of itself within a clock time. The configuration time of chaos computing chips is millions faster than that of FPGA. The common notion about constructing dynamic logic computing is that "This can only be achieved through strongly nonlinear thus typically chaotic characteristic" and "Note that nonlinearity in the processing units is clearly necessary for various Boolean implementations." So from 1998 to 2008, most works of the scholars of the same fields focused on the research of harnessing the nonlinear chaotic system to construct dynamic logic architecture. But chaotic systems which always show irregularity are very complicated and sensitive to the system parameters and initial conditions. Obviously, these characteristics bring disadvantages to the designing of dynamic logic computing chips with lower computing cost and high robust. If we, could find better schemes to realize dynamic logic computing, then the designing of reconfigurable chips will be largely simplified and their stability and reliability could be improved.Centered on the designing schemes of more simple, robust, flexible dynamic logic gates and their circuit implementations, this thesis put forward the schemes of harnessing and synchronizing dynamical system to design dynamic logic gate, given sufficient conditions that could guarantee the synchronization and parameter estimation when the system parameters are uncertain, realized the dynamic logic computing based on linear systems. Furthermore, this thesis proposed the algebraic logic computing to construct dynamic logic gates based on algebraic operations (addition, subtraction, multiplication and division). We proposed an analysis method, i.e. curve-intersection-based method, to design and analyze the dynamic logic gate distribution. Based on algebraic logic computing, this thesis gave a two-well model that could transform between all the 16 logic functions and solve the classical XOR classification problem.The main work and contributions of the present thesis are as follows:(1) Based on the harnessing linear dynamical system and threshold mechanism, the schemes of constructing dynamic logic gates were proposed. The logic computing element could transform flexibly between different logical functions by controlling system parameters. On this basis the realization of bit-by-bit arithmetic addition operation and memory were discussed and the concept of linear system computing was proposed. The linear system computing has apparent advantages over the chaos computing in the aspects of designing and manufacturing of new type of reconfigurable logic chips, reconfigurable processors and reconfigurable integrated circuits. The costs (structure cost and energy cost) of computing elements based on linear system will be less than those based on chaos computing. Linear system is not sensitive to initial conditions and system parameters, so the linear systems are more suitable to construct robust logic gates than chaotic systems for practical applications.(2) Since the linear synchronization errors could change with the varying of the system parameters, we proposed the computing schemes to realize the dynamic logic gate based on synchronizing linear systems. Based on the dynamic logic gates of synchronization schemes, a potential advantage is that the logic control could be realized at long distances, i.e., the operator could vary the control signals at long distance and easily realize the transformation of different logic gate functions more flexibly. Furthermore we studied the parameter estimation and logic gate designing based on synchronization when the parameters of the drive system are unknown. The idea of the parameter estimation based on synchronization was firstly proposed by German professor Parlitz. Many papers based on this idea have been published and Parlitz's paper has been cited more than 100 times for the past 10 years. We found that this idea was wrong, gave the counterexample. Further, based on Gram matrix theory, we systematically solved the conditions problem which could guarantee the identified parameters converged to the true values.(3) We proposed algebraic logic computing to construct dynamic logic gates based on algebraic operations (addition, subtraction, multiplication and division), which can emulate different logic gates and perform different arithmetic tasks and further have the ability to switch easily among different operational roles by changing the control instruction. We studied the multi-input multi-output dynamic logic gate, analyzed the effects of noise on logic gates, compared its differences and similarities with chaos computing and linear system computing, and gave the corresponding circuit implementations to illustrate the effectiveness and the feasibility of the proposed schemes. Compared to the chaos-based and the linear system based computing schemes, the algebraic logic computing avoids the complicated dynamical computation of dynamical system, the initialization of states and evolution processes in designing elementary gate units. The proposed methods could be used to construct and realize more flexible, more robust and lower cost reconfigurable dynamic computing devices.(4) We proposed the schemes of constructing reconfigurable dynamic logic gate by using the two-well potentials and algebraic operations. Through the varying of the width of the wells, the distance of the two wells and the positions of the two wells, we realized the transitions between 16 logics for the dynamic logic gate. We analyzed the distributing relations of different logic gates, discussed the influences of noise and further gave the corresponding circuit. Since the proposed scheme realized the transitions between all the 16 logic functions by using a single computing element, if it is used as a classifier, then the proposed scheme could be used to solve the classical XOR classification problem successfully. The classical XOR classification problem had brought the depression of the research of neural network more than 10 years. In order to solve the XOR classification problem, it often needed two-layer or three-layer above perceptions (at least 9 parameters) traditionally, while our proposed method only needs a logic element and only needs to adjust two parameters.(5) In the analysis and designing of static logic gates, a well-known simplification method is the Karnaugh map analysis method. Then what is the basic analysis method in the designing process of dynamic logic gates? This is a problem. This thesis discussed this point. We proposed an analysis method—curve-intersection method which could not only analyze the different distributions of logic gates, but also analyze the effects of noise. Using the proposed analysis method, we can know how to vary the control parameters in order to achieve different logic functions. All of the existing designing schemes of dynamic logic gates could be analyzed by the curve-intersection analysis method, thus we provided a basic, simple, intuitive and visual analysis method for the research on the dynamic logic gate.Taken as a collection, this paper studied the reconfigurable dynamic logic computing systematically and gave a series of schemes and the corresponding circuit implementations. The proposed schemes have transparent physical meanings, model simplicity, and are easier to be understood by engineers. Not only do they deserve deep research in theory, but also does it have better application values for engineering for the development of reconfigurable integration circuit chips.