Design Of Low Power Standard Unit Circuits

With the rapid development of integrated circuit technology, the feature size shrinking and the continuous improvement of circuit integration and working frequency, power consumption has become the main challenge of integrated circuit design following speed and area. Digital logic circuit design methods can be classified as AND/OR/NOT based Traditional Boolean(TB) logic and AND/XOR based(or OR/XNOR) Reed- Muller(RM) logic. Because TB logic is more mature, almost all of the circuit implementation and corresponding EDA tools are based on the TB logic. The current challenge of the integrated circuit design is deemed partly caused by the logic design method. Research shows that the RM logic is of the advantages in chip area, speed and power for some circuits. Although there are much RM logic research in recent years, there is rare research on standard unit circuit design, especially in low power standard cell research targeting RM logic circuit design. In this dissertation, the low power standard unit circuit design targeting RM logic is studied. The dissertation consists of the following aspects:1. Existing various AND gates, XOR gates, OR gates and XNOR gates are analyzed and the cascade AND/XORs and OR/XNOR gates are as comparative objects against the proposed circuits based on transistor level.2. Due to the advantages of Pass Transistor Logic( PTL) and Transmission Gate(TG) Logic, proposed the transistor level AND/XOR and OR/XNOR Gates are proposed.3. Under the Linux, 55 nm process environment, the Cadence tools are used to carry out the schematic and layout design for the proposed circuits. the Calibre tool is used to do DRC, LVS and the parasitic parameter extraction. HSPICE is employed to simulate the circuit performance and comparison is made against the cascaded circuits. The experimental results show that the improvement of the proposed AND/XOR gate circuit power consumption and the power delay product(PDP) is as high as 26.67% and 31.25% respectively. while the OR/XNOR gate is as high as 21.88% and 38.61%,respectively.4. Benefiting from the advantages of complementary static CMOS circuit structure, the corresponding transistor level AND/XOR and OR/XNOR gates are proposed. The simulation is carried out under three different processes, 0.13 nm, 0.18 nm and 0.24 nm, with HSPICE. Comparison is made against the corresponding cascade structures on the performance analysis and comparison. The experimental results show that the proposed circuits have good performance under three different processes.