Low-power high-performance dynamic circuit design for ultra-deep submicron technology

Recently, power consumption has become one of the most important design concerns in VLSI system development, and dynamic logic has been widely used in high-performance design to achieve multi-gigahertz performance. Conventional dynamic logic has several design issues such as high power consumption and signal integrity in ultra-deep submicron technology.; Dual-rail dynamic logic provides high fan-in logic gates and logic synthesis flexibility. However, it consumes more power than single-rail dynamic logic. Modular charge recycling pass transistor logic is proposed to resolve the preevaluation discharge problem of previous charge recycling logic and to achieve low-power and high-performance.; When dual threshold voltage technique is applied to domino logic to improve performance, a keeper transistor should be properly sized. On the other hand, the keeper transistor affects evaluation time and active/leakage power consumption. Based on the effects of the keeper transistor, a low V_t selection algorithm is introduced for high performance with noise and power constraints.; Conventional transistor sizing algorithms for domino logic mainly focus on performance improvement but do not address noise issues due to subthreshold current. A new keeper transistor sizing method is introduced to meet the noise constraint. Noise constrained domino logic synthesis with optimal keeper transistor is also proposed to reduce power consumption.; For a wide fan-in logic gate with low V_t, a large keeper transistor is required to meet the noise constraint. However, the large keeper transistor degrades the circuit performance. To resolve this problem, skew-tolerant high-speed domino logic is proposed. Based on complete timing analysis, optimal timing strategy is developed to allow wide skew-tolerant window. Gate voltage controlled keeper structure is also devised, which can optimize performance, noise-, and skew-tolerance.; Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference.