Research On The OTP Logic Arrry Circuit Design

With the fast development of microelectronics, programmable logic array has gone through several changes, from the first beginning of PAL to PLA, then to the most widely used device CPLD and FPGA. With the increasing attention on information security, OTP FPGA has been widely researched in kinds of field. While, owing to the difficulty and complexity, it’s not easy to research OTP FPGA directly. That’s why lots of researchers decide to divide the whole work into several steps, and study it step by step to develop high-performance OTP FPGA finally.This paper aims to design an OTP logic array circuit, verifying the feasibility of applying the new OTP programmable unit with independent intellectual property. The circuit designed by this paper has several parts, including the design of OTP programmable unit, programmable circuit, reading back circuit, logic implementation circuit, layout design and the test of chip. After the description of the breakdown principle of the OTP programmable unit, this paper puts out a new OTP programmable unit structure, and elaborate the principle of operation. After that, the whole design plan of this circuit is presented. In the design of this circuit, voltage conversion part ensures that high voltage signal can be read safety by the internal circuit. Two stage charge pump could transfer the high voltage signal to the programmable unit port safety and stability so that the probability of failure to work normally will be reduced with the instability of high voltage signal. Several dimensions encoding can reduce the delay of the operation with the arrangement of logic array. Reading back part can get the right programming data under the help of pulse expansion circuit and sensitive amplifier. In addition, two stage DICE latch can latch the data read by reading-back circuit and convey it to the outside port safety. For logic implementation circuit, any combinational and sequential function can be implemented by using the CLB logic block, which is connected to the programmable unit. In the layout design, this paper has proposed several notes about special problems, and given the corresponding solutions, when the whole layout is finished, parasitic parameters will be extracted, then run the post-simulation, analyze the result and give the feedback. As a result of constant correction, the purpose of design has been realized finally.After tape-out, test the corresponding function of the chip, including the OTP programmable circuit, reading-back circuit and logic implementation circuit. According to the testing result, the whole functional block work normally, it shows that the OTP logic array circuit design by this paper has met the expectation, and the design goal has been realized.