| Reconfigurable computing is becoming an important part of research in computer architectures and software systems. By placing the computationally intense portions of an application onto the reconfigurable hardware, that application can be greatly accelerated. Gains are realized because reconfigurable computing combines the benefits of both software and ASIC implementations. However, the advantages of reconfigurable computing do not come without a cost. By requiring multiple reconfigurations to complete a computation, the time to reconfigure the hardware significantly degraded performance of such systems. This thesis examines a complete strategy that attacks this reconfiguration bottleneck from different perspectives. Compression techniques are introduced to decrease the amount of configuration data that must be transferred to the system. Configuration caching approaches are investigated to retain configurations on-chip. Configuration prefetching techniques are developed to hide reconfiguration latency. Reconfiguration overhead is virtually eliminated by using these techniques. |
