Research On The Design Methodology Of Application Specific Coarse Grained Reconfigurable System On Chip

With the rapid development of VLSI technology and the big progress of So C design methodology,various types of embedded So C devices’ applications is growing to the diversity direction.The design technology of application specific coarse-grained reconfigurable So C,which based on reconfigurable instruction sets processor(RISP), as proposed a solution which combines reconfigurable technology, application specific instruction set processor(ASIP) and multicore processors So C(MPSo C).Now, the design technology of application specific coarse-grained reconfigurable So C is a critical issue in the reconfigurable So C research field.This paper studies on the key technologies of the architecture design method for coarse-grained reconfigurable So C(CGRSo C). The main contributions are listed as follows:(1)Template-based design methodlogy of CGRSo C is proposed.Since the traditional design methodlogy of MPSo C has large design space exploration and high design complexity,an template-based design methodlogy of CGRSo C is proposed in this paper.The template,which not only reflects the feature of the application’s calculation mode, but also reflects the feature of coarse-grained reconfigurable architecture, is built and described in two levels,one is MPSo C architecture template,and the other is coarse-grained reconfigurable architecture template,and all parameters can be configured.As a result of instantiated the design templates, cryptographic application specific multi- reconfigurable instruction sets processor So C(Multi-RISP So C) is putforward, which will RISP design space exploration limited to a certain extent, making the RISP that has a strong performance reconfigurable technology also has flexible programming features.(2)Design of the application specific reconfigurable instruction sets processorReconfigurable architecture for application customization is an effective approach to enhance operational performance and increase operational efficiency of resource use. This paper studies on the method of application features analysis and functional units customization, and an architucture of reconfigurable instruction sets processor, which based on functional units customization is proposed. The architecture uses standard processing unit and application customization unit co-processing the reconfigurable pipeline processing structure, which can effectively save reconfigurable hardware computing resources, and improve pipeline processing speed. This paper implements a custom design of block cipher specific reconfigurable instruction set processor(BCSRISP). Experimental results show that, compared to using only the basic processing unit SPE, synergistic using of SPE and CFU can gain better acceleration effect for cryptographic processing. Meanwhile, in order to avoid the effects of physical factors such as circuit layout and semiconductor technology, we analysis the relationship between the amount of resources and accelerate performance ratio, using the number of functional units as a measure.(3) Design of reconfigurable interconnect technology for Multi-RISP So C and FBEA-BLESS.This paper firstly analysis the various interconnection strategies that described in the architecture template, and then combines the constraints of application’s feature and design complexity, using mesh-based network and crossbar switch architecture to complete the interconnection architecture of Multi-RISP So C. Due to livelock and delay in current bufferless router design, a flit-switch bufferless router based on encoding allocation(FBEA-BLESS), is proposed in this paper, which can reduce the delay of critical path through two stage switch allocation with non-deflection allocation and deflection allocation. The Go-Stop-Steer(GOSS) strategy was used to avoid livelock in the network. Simulation results show that, compared with BLESS-3 and other bufferless routers, FBEA-BLESS gets a better performance on throughput, zero load latency, and frequency,which is proved be very suitable for design of Multi-RISP So C.(4) Design of hierarchical memory for Multi-RISP So CThe generate efficiency and quality of configuration information affect the operating results of coarse-grained reconfigurable So C. Since the traditional approach treat the configuration memory as a whole, and it has low efficiency because of each processing unit needs to read configuration information from the memory.A hierarchical structure of configuration memory for cryptographic specific coarse-grained reconfigurable So C is proposed in this paper,which divided configuration information into separate operating configuration information and interconnect configuration information, and then generate the configuration information based on the context. Experimental results show that the configuration information generation method proposed in this paper can reduce power consumption of 23.7% ~ 32.6% while keeing the the same performance. For different applications, when the application can not reconfigure the interconnect status, the interconnected information is a great proportion of configuration information, which will bring more power improvement.(5)Design and Implementation of EVMPSo C-E.Based on above study and the achievement of our group, an embedded visual media processing So C(EVMPSo C-E) is designed and implementated in this paper, which verify the the design ideas and concepts above partly. Finally, through an application example, the calculation of EVMPSo C-E performance and efficiency shows its efficiency and availability.