Design And Optimization Of Configuration-Path Sub-System In Coarse-Grained Reconfigurable Processor For Radar Applications

Because of the combination of flexibility and efficiency, reconfigurable system is suitable for implementing various computation-intensive Radar signal processing with high complexity and large amount of data. However, with the growing performance requirements of Radar applications, the computational resources of coarse-grained reconfigurable architectures increase rapidly, which leads to larger amount of context and sharply growth of context transmission time, as well as reduces the overall system performance. Therefore, setting up an efficient context management mechanism plays a very important role in improving the reconfiguration efficiency of reconfigurable systems.Based on a typical coarse-grained reconfigurable processor used for Radar applications, this paper focuses on the problem of long configuration transmission time caused by large amount of configuration contexts. Firstly, the Radar signal processing is analyzed, and the features of kernel sub-algorithms is extracted. Secondly, based on the hierarchy configuration cache structures, the basic architecture of configuration sub-system is proposed according to the hardware features of RASP and operation features of kernel sub-algorithms, then performance of the configuration sub-system is evaluated. Thirdly, according to the analysis of performance, the features of configuration flow of the Radar algorithms is analyzed and redundancies of multi-tasks and multi-sub-tasks are extracted, then the hierarchy configuration organization strategy is proposed. At last, with efficient control of decompressing time, a configuration compression approach based on dynamic pattern matching that can efficiently reduce the configuration size is proposed.Experimental results show that based on SMIC 40nm process and 500MHz frequency, the proposed hierarchical organization policy for configuration contexts and configuration compression method based on dynamic pattern matching can reduce the configuration size of kernel algorithms to 40% or less of the original, while the decompression time only costs 6 ns. In the case that the configuration cache overhead is reduced by 25%, the hit rate of context group cache increases by 5%～8%, and the hit rate of array context cache increased by 5%-16%. Configuration performance of the optimized RASP is improved to 2.6 times than before, higher than SIMD and dictionary configuration compression approaches. For FFT algorithms of same points, performance of the optimized RASP is more than five times that of other reconfigurable processors. For matrix inversion algorithms of the same order, performance of the optimized RASP is more than three times that of other reconfigurable processors. What’s more, optimized RASP has better system flexibility, for it can achieve better performance in a wide range of parameters.