Soc Reconfigurable Computing Components Of The Asynchronous Reconfigurable Computing Array Design

Parallel computing in SoC realized by hardware is an appropriate way to good performance processors, especially to embedded system. But compared to instruction-based processor, hardware-processor loses application flexibility while takes advantage of high computing speed. Meanwhile, though instruction-based processor success wide and far because of enormous flexibility, throughput is still the limitation by their sequential nature of operation (classical Von-Neumann bottleneck). Reconfigurable Computing (RC) architecture, which is divided into coarse grain and fine grain, supplies a gap of that. To overcome the shortages of both coarse and fine grain RC architectures, a novel RC architecture was proposed.Novel RC architecture based Reconfigurable Computing Unit (RCU) works as a SoC IP, affording computing-intensive applications mainly of encryption and DSP. In . RCU, Reconfigurable Computing Array (RCA) burdens computing tasks. Installed around that, Data Stitcher (DS) is RCA's local controller, and DSes are managed by DCC (Data Computing Controller in RCU).The Reconfigurable Computing Array (RCA) is a fine-grain asynchronous device of reconfigurable computing and consists of Logic Cells surrounded by NN (Nearest Neigbouring) channels. After the configuration of operation and route, Logic Cells from RCA form the structure of asynchronous mircopipeline. RCA is designed as an asynchronous architecture, the problem of power consumption has been eased off. Also, without clock, RCA can be totally prevented from the inferiority of clock-skew. As we adopt DSDVCSL in the design of operation circuit of Logic Cell, the design flow follows a novel way named digital/full-customer mixed.Compared with commercial FPGA, our RCA achieve high performance in encryption computing application.