Design Of Configuration-path Caching In Coarse Grained Reconfigurable System For Baseband Signal Processing

Because of their high flexibility and high performance,reconfigurable processors are suitable for implementing computation-intensive baseband signal processing with large amount of data.However,with the growing kinds of algorithms and the growing performance requirements in baseband signal processing,the computational resources of Coarse Grained Reconfigurable Architectures increase rapidly,which leads to larger amount of contexts and sharply growth of context transmission time.In this dissertation,we focus on the following tasks to improve the efficiency of reconfiguration:First,the process of baseband signal processing is analyzed,and the features of kernel sub-algorithms are extracted.Then we select appropriate implementation for the kernel sub-algorithms,and we also analyze the hardware architecture and the configuration of the typical Coarse Grained Reconfigurable system for the baseband signal processing.Secondly,we analyze the organization form of the hierarchical index of configuration contexts and the compression method based on pattern matching.Then the storage characteristics of configuration contexts are summarized,and the basic structure of the dual Cache for hierarchical configuration is designed,and its hardware parameters are determined.Thirdly,according to the Cache structure,a dynamic scheduling mechanism is designed,which is divided into system level and module level.The scheduling mechanism based on dual Cache subsystem is described,and the existing problems of Cache replacement are expounded.Then,the characteristics of configuration contexts are extracted,and the advantages and disadvantages of the common Cache replacement strategies are analyzed.A dynamic function scheduling mechanism based on priorities is proposed,which greatly improves the hit ratio.Finally,we design the dynamic decompression method,and determine the configuration information decompression program.Experimental results show that based on SMIC 40nm process and 445MHz frequency,the dual Cache for hierarchical configuration and its dynamic scheduling mechanism in this paper make the hit rate of L1 layer Ccache increased by 1.8 times,and the hit rate of L2 layer Cache increased by 1.4 times.What's more,the power consumption of Cache accounted for only 9.2%of the system power consumption.For FFT algorithms,performance of RASP is more than five times that of other reconfigurable processors.For matrix inversion algorithms,performance of RASP is more than two times that of other reconfigurable processors.