Study Of Reconfigurable Computing For Active Storage Service Processing

Active storage means the storage system can process data by itself, and it is a promising solution for data-intensive applications like data mining, multimedia processing and data security. The previous research efforts on active storage utilize spare processing power of the general purpose processor on the storage controllers. The commercial off-the-shelf product-based hardware solution for storage controllers results in high power consumption and high cost. The SoC (System on Chip) hardware solution for storage controller designs has the benefits of good customizability, low power and high performance, and now it has become the trend. Because the embedded processors in SoCs run at lower frequency than general purpose processors, it's quite difficult for SoC-based storage controllers to process active service efficiently. Dedicate hardware accelerators can be used to increase computation power, but this solution is lack of flexibility.A reconfigurable computing solution for active storage is presented. The basic idea is incorporating reconfigurable hardware accelerators in storage controller SoCs for high performance and flexible active service processing. Based on Xilinx SoPC (System on Programmable Chip) platform, the hardware coprocessor and accelerator schemes are studied. The experimental results show that the coprocessor system achieves good performance, but this scheme consumes certain CPU processing power, so it's the right choice for computation-intensive applications. Due to high bus transfer latency and interrupt service overhead, the PLB (Processor Local Bus) accelerator works less efficiently. The MPMC (Multi-Port Memory Controller) accelerator utilizes low latency direct connection with the system memory via on-chip switch fabric, and it achieves better performance than the PLB accelerator. The two accelerator schemes can use DMA to transfer data, their performance is independent of the CPU power, and they are suitable for I/O intensive service processing.The reconfigurable SoC design is different from static digital system design, and additional function blocks should be introduced to control the reconfigurable hardware. Several issues about reconfigurable SoC design are addressed, it includes memory address mapping for reconfigurable accelerators, post-reconfiguration circuitry reset and signal passing between static and dynamic hardware blocks. Experimental results show that the reconfigurable hardware can achieve the same efficiency as the static circuitry, meanwhile it saves chip area. A drawback of reconfigurable computing is the large reconfiguration latency (typically over 10 ms). According to experiments, the configuration data transfer rate between system memory and configuration controller via PLB bus dominates the overall configuration throughput. A configuration controller with a partial bit-stream cache is presented. When the cache is hit, the reconfiguration speed can increase by a factor of 10. The cache uses fully associative organization and a cache replacement algorithm is proposed. The replacement algorithm considered not only the recently used frequency but also the chip area of the dynamic function block.Configuration scheduling is a well known technique for reducing reconfiguration latency when multiple Reconfigurable Processing Units (RPUs) are available on the chip. A task scheduling and configuration scheduling algorithms are presented for active service processing. The task scheduling maintains the maximum overall performance for multiple parallel tasks first, and then tries to speed up a single task according to first in first served principle if possible. The proposed configuration scheduling includes hybrid configuration prefetching and configuration caching algorithms. From the simulation results, both the partial bit-stream cache and the configuration scheduling algorithm can reduce the configuration latency and improve the system performance.Putting all above together, an active storage controller prototype design is implemented on Xilinx ML509 board (equipped with a V5 LX110T FPGA device), and the SoC design integrates 4 reconfigurable MPMC accelerator to process active service. The prototype controller uses a RAMDisk to emulate a hard disk. In the experiments, a server machine is connected with the storage controller via Ethernet using iSCSI protocol, and a service binding method for T10 OSD SCSI protocol is presented. Active service applications such as data security, data compression and image processing are used as case studies. The experimental results show that the reconfigurable computing solution can greatly improve the system performance and reduce the service task response time comparing with the software solution on a 400MHz PPC440-based SoC design.