An Approach For Testing FPGA TEMAC Core Based On BIST

With the rapid development of integrated circuit technology,the integration of FPGA(Field Programmable Gate Array)chips has been continuously increased.TEMAC(Tri-Mode Ethernet MAC)is a network processing IP(Intelligent Property)core which is embedded in FPGA chips.TEMAC can implement the functions of a general MAC(Media Access Control)controller.The MAC mainly controls the allocation of shared channels to ensure that the transmission medium can effectively transmit Ethernet frames.Efficient testing of the FPGA TEMAC core is a worthwhile research direction.Because the foreign advanced FPGA manufacturers keep the test method as a secret,the corresponding literatures are not available,while domestic related research is still weak.In order to support the TEMAC core test for own-made FPGA development and to ensure the reliability of the TEMAC core for imported FPGA,it is necessary to carry out the test for TEMAC cores embedded in the FPGA.This paper studies the protocol and communication theory of Ethernet,analyzes the function and structure of TEMAC,and explores the functional test method and performance test method of TEMAC cores.BIST(Built In Self-Test)is a test technology that uses FPGA chip programmable resources to test its own internal circuits.BIST is the mainstream technology for researching FPGA device testing in domestic and foreign.By using the programmable resources inside the FPGA chip to achieve the functional test and coverage of the TEMAC core,it can effectively solve the problem of the current high-end FPGA chip testing technology blank,and provide a support for reliable use of the embedded TEMAC core.This is very important for the embedded TEMAC core test and BIST technology research.The combination of the embedded TEMAC core test and BIST technology is a exploration in a new field.This paper studies a test method of TEMAC based on BIST structure and builds a test structure for TEMAC communication.The BIST structure for TEMAC internal function module is designed.This method can test the main functions of TEMAC including Data sending,Data receiving,HOST bus,Flow control and Address filtering.The BIST structure and test frame and protocol loopback path for performance test are designed for the characteristics of TEMAC performance test.This method can test the network performance of TEMAC according to the RFC2544 standard.The BIST structure can flexibly configure test time,test frame length and number of test frames,and automatically perform performance tests under different data frame lengths specified in RFC2544,can test and count the three network performance indicators of throughput rate,packet loss rate and time delay.This article builds a test system that includes hardware and software.In this paper,the BIST test method is applied to the test of a TEMAC embedded in a high-performance FPGA chip.The experimental results show that the functional test of the BIST test method covers the main functions of TEMAC module.The performance test meets the accuracy requirements.The test accuracy of throughput and packet loss rate is less than one in ten thousand of that of the industrial grade network tester,and the time delay test accuracy is higher than that of the industrial grade network tester.The throughput accuracy,packet loss rate,and delay test accuracy are gradually close to the ideal test results as the length of the test data frame increases.The test results prove that the test method in this paper is effective and has high precision.