| The demand for Analog and RF ICs for wireless communication is growing rapidly in recent years. This propels the development of low cost implementation such as RF BiCMOS technology, allowing the design of wireless circuits with complex CMOS functionality. The objective of this thesis is to develop a RF BiCMOS process by integrating RF bipolar transistor with a standard 0.35mum CMOS process.; This BiCMOS process is implemented using an existing 0.35mum CMOS production technology from Asahi Kasei Microsystems (AKM). The proposed process incorporates the original processing procedures and design rules of the CMOS process, and three additional masks are added to form the RF BJT. The additional costs and alterations on the original process are minimal, and this technology is designed to co-exist with the original process.; Design considerations related to the poly-emitter bipolar transistor characteristics and the process flow of BiCMOS integration are discussed. Two-dimensional process and device simulations for device optimization, and three-dimensional device simulations are presented. The DC and AC performance of the fabricated test structures was electrically characterized. The bipolar transistor showed an unity-gain frequency (ftau) of 18.5 GHz and collector-emitter breakdown (BVCEO) of 3.1V.; The AC performance is comparable to previously published results for BiCMOS processes. However, the cost is significantly lower because this process only uses single poly, implanted base and with no trench isolation. In conclusion, this BiCMOS process offers good RF performance, low cost and is compatible with standard CMOS technology. |
