Research Of High-speed Optoelectronic Integrated Receiver Based On Standard CMOS Process

For high-speed, low-cost optical fiber communication, one of the bottlenecks ismonolithic integration. Compared to the monolithic CMOS optoelectronic integratedreceiver, the hybrid-integrated photo-receiver, not only has the great cost, but also hasthe parasitic elements caused by packaging, inter connection between differentmodules, electromagnetic interference, and noise of environment. OEIC technologycan solve the above problems and also has advantages of reducing chip area,achieving higher yield and higher reliability. For the pursuit of comfortable life,optoelectronic integrated receivers based on standard CMOS technologies have beenresearched much recently. In order to overcome the bottlenecks of the CMOS receiver,the following researches and experiments are presented.As the first receiving device, the photodetector’s performance directly affects thequality of the signal received. We use the P active region, N-well and P substrate inUMC0.18μm standard CMOS process to form a PN junction as photodetector. Usingthe spatial modulation structure can improve the physical bandwidth of semiconductor.A spatially modulate photodetector modelled and simulated through Silvaco’s Atlassoftware indicated that the designed photodector has an intrinsic physical bandwidthof942MHz, and a responsivity of227mA/W.The transimpedance amplifier for optical receiver adopted a common sourcedifferential structure with constant current source as loads. Differential structure isbenefit to eliminate interference. The gain and bandwidth of transimpedance amplifierare61.51dB and1.078GHz, respectively.A limiting amplifier structure with resistance as loads was used as the mainamplifier circuit for optical receiver. As cascading limiting amplifier will narrow thebandwidth of LA, the inductance sharpening technology was employed to extend thebandwidth.Considering the effects of oscilloscope and other test-related instruments, anoutput buffer stage driving50Ω load resistance and10pF load capacitance wasdesigned. The whole OEIC circuit was simulated with SMIC0.18μm standard CMOSprocess. The pre-simulation reuslts showed that the designed optical receiver has gainand bandwidth of89.94dB and1.682GHz. The output eye diagram open clearly when it receives a pseudo-random signal sequence of1.25Gb/s.In this design we use Cadence’s Virtuoso and Spectre software to draw layoutand simulate the circuit of OEIC.