Wideband Phase and Frequency Synthesis Techniques for Wireless Communication Circuits

In this dissertation, we present three wide bandwidth phase and frequency synthesis techniques that can be adopted in wireless communication circuits.;Wide bandwidth phase modulator is one of the fundamental building blocks for low power wireless transmitter architectures, such as polar transmitter or out-phasing transmitter. Lower power consumption can be achieved because instead of linear power amplifiers, they adopt nonlinear power amplifiers where no back-off operation is required. However, currently the adaptation of these architectures is limited to narrowband communication systems partly due to the difficulty of generating a phase modulation signal that is wideband enough. In this dissertation, we present an open-loop wide bandwidth phase modulator with a phase quantization noise cancellation technique. The modulation is achieved outside the PLL, so the modulation bandwidth is not limited by the PLL loop bandwidth and can be very wide. A 2.4-GHz phase modulator prototype targeting at IEEE 802.11g WLAN system is implemented in TSMC 0.18-mum CMOS technology. The proposed phase quantization noise cancellation technique effectively reduce the peak out-of-band noise by 7-dB so that the measured peak out-of-band phase noise is -49-dBr when transmitting a 20-Mb/s GFSK signal with 3.2% r.m.s. error. The current consumption for the transmitter excluding the output buffer is 34.5-mA under 1.8-V supply voltage. Since a big portion of the transmitter is digital, lower current consumption can be expected when migrating to a more advanced technology.;Secondly, a 2-MHz Delta-Sigma fractional-N frequency synthesizer based on a staggered switching fractional frequency divider is presented. The phase interpolator based fractional frequency divider provides lower instantaneous phase error at the phase frequency detector input and hence lowers the Delta-Sigma quantization noise, so that the synthesizer loop bandwidth can be increased. To suppress fractional spurs due to phase interpolator phase errors, a digital spurious tone suppression technique is adopted. The frequency synthesizer is implemented in 0.18-mum CMOS process, and it operates at 2.1-GHz carrier frequency with 2-MHz bandwidth. 6-dB of spurious tone reduction is observed in measurement. Excluding the output buffer, the synthesizer consumes 33.9-mA and is capable of transmitting 4-Mb/s GFSK signal.;Lastly, two purely digital charge pump mismatch shaping techniques for Delta-Sigma fractional-N PLL are proposed. They improve a previously proposed charge pump linearization technique that demonstrated 8-dB reduction in spurious tones caused by charge pump current mismatch. Both techniques suppress spurious tones by randomizing the residual charge pump mismatch error power. The second technique further spectrally shapes the residual charge pump mismatch errors to suppress close-in phase noise. No spurs are observed and -122-dBc/Hz phase noise is achieved at frequency offsets lower than 10-kHz in simulation.