Test and diagnostic schemes for local interconnects of Xilinx Virtex FPGAs

Most of the previous work on testing FPGA local interconnects was applicable to FPGA families simpler than the Xilinx Virtex FPGA family.; This work presents a new built-in self test (BIST) scheme to test the local interconnects of the Xilinx Virtex FPGAs. It presents the first heuristic methodology that can derive a minimal or near minimal set of test configurations (TCs) for the Virtex FPGAs local interconnects. A graph model of the local interconnects based on bipartite graphs is presented. The fault models taken for this test are common ones used for interconnects. A set of test vectors and an analytic proof of fault detectability is also given. An edge-coloring algorithm is developed for deriving a minimal or near minimal set of TCs to verify the integrity of local interconnects. A key result of this thesis work is that a minimal set of 26 TCs for Xilinx Vertex FPGAs is derived. Our test is therefore optimal with respect to the required number of TCs.; Furthermore, two fault diagnostic schemes based on the proposed BIST scheme are also presented for two separate fault diagnostic applications: fault-tolerance and manufacturing testing of FPGAs. These proposed diagnostic schemes reuse the previously derived TCs that were developed for the regular test scheme.