Research On FPGA Interconnection Automation Test Method

Field Programmable Gate Array is a kind of chip that can be configured very fast in a number of times and has been widely used. FPGA interconnecting resources include wire segments and programmable interconnecting points (PIPs). These resources are integral to the functionality of FPGAs and thus testing them is pretty important. Wire segments spread along the horizontal and vertical channels, while PIPs reside in Switch Matrixes, Input Multiplexers and Output Multiplexers. Wire segments and PIPs in Switch Matrixes are categorized as global resources; PIPs in Input Multiplexers and Output Multiplexers are categorized as local interconnects.Fault coverage, the number of test patterns and automation are the benchmarks for FPGA test methodology. The FPGA industry leverages a semi-manual method. They design every pattern very carefully to make sure the number of patterns is minimized. The academic filed tends to utilize more automated methods. In terms of testing global interconnects, prior papers relied on the divide-and-conquer strategy. They divide all PIPs into four groups, namely the horizontal group, the vertical group, the left diagonal group, the right diagonal group. And then they use an algorithm to test each group. However, interconnects in new FPGA architectures are far more complex; irregular PIPs which cannot fall into any of the four groups begin to exist in new FPGA architectures. In terms of testing local interconnects, previous papers are focused on island-based FPGAs, while the mainstream FPGAs are based on the tiles. Hence, previous methods lend little help to testing contemporary local interconnects. Considering all the problems above, this paper is focused on the following aspects:First, a BIST (Built-in Self Test) circuit is realized. This circuit is pretty simple and occupies very limited logic resources. This circuit is used to counter the limitation of inadequate IOBs and stuff more wires under test into one configuration file.Second, after analyzing the local interconnects in FPGAs, a method that can cover local resources with the minimum number of patterns is proposed. With this method, every tile is configured in exactly the same way and concatenated. This method exhibits regularity, simplicity with minimum configurations.Third, a method to test global interconnects in new FPGA architectures is proposed. Irregular interconnects begin to exist in new FPGA architectures and no papers have brought up methods to cover it. This paper brings up a new method that can cover special interconnects and yields a high coverage. This method could not only cover regular interconnects, but also irregular ones.Simulation results show that the BIST circuit works properly. The method proposed targeting local interconnects is applied to FDP3P15and experimental results show that local interconnects can be covered with24configurations. Experimental result also show that the method targeting global interconnects can be utilized to cover global interconnects for FDP4P1K and FDP4P7K both with99%coverage.