Design And Implementation Of Process Level Dynamic Partial Reconfigurable System Based On Xilinx Virtex-Ⅱ FPGA

Reconfigurable computing technology combines the advantages of GPP (General-Purpose Processor) and ASIC(Application Specific Integrated Circuits), providing the hardware efficiency and software programmability in one platform. It is one of the hot topics of current computer research. As the most recent development of reconfigurable computing technology, dynamic partial reconfiguration can reconfigure a part of the reconfigurable logic device while other parts of the system continue to operate, enabling the parallel execution of running tasks and reconfigurations. It can efficiently utilize the reconfigurable resource and improve flexibility of the reconfigurable computing system.Programmable logic devices with partial reconfigurable feature are the guarantee to the dynamic partial reconfiguration technology. Currently, the most widely used device is the SRAM-based FPGA(Field Programmable Gate Array), capable of repeatedly reprogramming. By loading different configuration data to FPGA, different hardware functionalities can be executed. Xilinx Virtex-II Pro Series FPGA is one of the key programmable devices supporting denamic partial reconfiguration.Xilinx Inc. has provided a rich set of documents for the dynamic partial reconfiguration technology realized on the Xilinx Virtex-II Pro Series FPGA. However, since the dynamic partial reconfiguration technology is fairly new, there is hardly a well proven design flow for reliable dynamic partial reconfigurable system development, which in some extent, slows down the popularization of the dynamic partial reconfiguration technology.The paper introduces how to use the ICAP (Internal Configuration Access Port) to reconfigure the encryption IP (Intellectual Property) modules on the OPB (On-chip Peripheral Bus), and implement the process level dynamic reconfigurable system on Xilinx Virtex-II Pro XC2VP30 FPGA platform in detail. The completed research work includes:(1) Setup a reliable module-based dynamic partial reconfiguration design method, including the establishment of the initial hardware platform, the partitioning and design of static and reconfigurable module, module generation and system assembly.(2) Use the slice-based bus macro to solve the key problem of the communication between static modules and reconfigurable ones. Considering the defects in efficiency of communication and signal control provided by the TBUF-based bus macro, the paper realizes the slice-based bus macro according to the system reconfiguration requirement. Experiment shows that the slice-based bus macro is more effective to control the operation of reconfiguration.(3) Following the proposed module-based design method, the paper completes the design and implementation of a dynamic partial reconfigurable sytem. The sytem achieves run-time reconfiguration on the XC2VP30 FPGA device. Experiments show that the system allows multiple design modules to time-share physical resources, improving the utility of FPGA hardware resources.