The Testing Of Virtex FPGA Interconnects

The function of FPGAs is becoming increasingly stronger and the complexity has been increasing along with the development of microelectronics technology at very fast speed and the scale of integrated circuit has been enlarged endlessly. Further more, the design period of FPGA devices has been shrunk by the designer who uses the CAD tools, but the difficulty has been increased. It leads to the increase in time and expense spent on the testing. The expense spent on the testing is about 40 percent of the total cost. The testing of FPGAs impacts not only the quality of FPGA devices, but also the design period and cost. The problem of finding the testing path is the first step as well as the most important step of interconnects testing. In order to reduce the workload and enhance the efficiency of testing with the precondition of enough testing coverage of FPGA interconnects, this paper presents a testing method by which the testing path is easy to find and the testing coverage achieved is more than 95 percent. In this method, the nodes on the testing path are set in an array and the Max-flow algorithm is used to find the testing path. This paper describes the principle and flow of the Max-Flow algorithm in detail. And then the proposed method is carried out by program. Thus, the problem of finding the testing path is solved.