Test Of Internal Resources For Virtex-II Fpga Based On Bitstream Readback Technology

In the last decade, the FPGA industry has developed rapidly.Increasing chip size and rich internal resources make the FPGA become one of the main platform of digital system development.With the function of FPGA is more and more powerful, more and more fields appear the figure of FPGA.We must ensure that the FPGA which applyed in system is high reliable before we use it. Especially for sensitive areas such as aerospace, medical, military and so on,we need to ensure it could perform specified functions without any error, otherwise it will cause inestimable losses to the entire project. Therefore, testing FPGA to ensure its reliability has become an inescapable work for us.After the design has been implemented in FPGA, the internal nodes are not visible.This will make it difficult for testing FPGA. Many scholars, at home or abroad, have presented some methods and solutions on this issue. In this paper, we proposed a new solution to test internal resources of Virtex-II series FPGA based on bitstream readback technology.The method could be used in other FPGA which supports bitstream readback function. The contents are divided into four parts shown as follows.(1) analyzing the underlying structure of Virtex-II series FPGA.Doing a detailed analysis on the configurable logic block’s various configurations and Interconnect resources(IR).(2) A method of testing configurable logic block based on bitstream readback technology is presented.(3) make detailed classification for hierarchical routing resources and on the basis of classification propose a method of testing interconnect resources based on bitstream readback technology.(4) Using the methods we have discussed above,test patterns have been configured for configurable logic block and interconnect resources in FPGA_editor software. Doing the experiment on the actual XC2V1000BG575 chip.Bitstream readback technology has improved FPGA’s visibility of internal resources. Testing method proposed in this paper has been practiced on the actual chip of Xilinx XC2V1000BG575. In the process of compiling configuration graphics we use Perl language tools which speed up the generation process of the configuration graph and reduce configuration time.