A Test Solution Of The Coverage Of Interconnects In The FPGA With Millions Of Gates

In recent years,domestic programmable logic devices have gotten a rapid development,and FPGA with millions of gates has achieved mass production.With the functions of programmable devices to enhance,and the distribution network of interconnect lines becomes more and more complicated,as a result,the work that designers test all of the interconnect lines has become increasingly difficult.At present,the research on programmable interconnect lines test has made a breakthrough in China,and the technology for testing switch matrix is becoming more and more mature,however,there is no specific plan for the test of interconnect integrity.Although applying the method for testing programmable nodes can help us to achieve identification of interconnect integrity indirectly,but for testing every type of interconnect line,the FPGA needs to be configured as many as thirty times,executing the test about all of the interconnect integrity needs us to configure a FPGA for more than one hundred times.Obviously,it is not appropriate to apply this test method to chip production.In the production process of FPGA,it is really necessary to find a way for testing the interconnect integrity.In this paper,the author takes a Xilinx FPGA in Virtex II series as a research object,and a kind of routing scheme with fewer configuration times and higher coverage rate is proposed.The writer also introduces a variety of programmable resources in FPGA briefly,and gives a brief analysis of the interconnect structure.And then according to the difference of the positions of interconnect lines,the design methods of different test vectors are given.For the interconnect lines between the switch matrix,the test vector is designed by XDL(Xilinx Design Language).What we should do at first is to decompose the interconnect lines and to establish corresponding model,then we need to search routing path by using graph theory and flow algorithm based on the interconnect model.At the end of searching the path,use XDL language compiler to route the path that we found,finally transform these text information into the test pattern,merge the routing path,optimize the layout,implement the test.For the interconnect lines between the switch matrix and the Slice,the test vector for them is designed by the macro.First,we can design a macro unit including some quick lines,then use Verilog language to package the macro unit,and establish position constraints for macro unit to cover all Slices,finally implement post place and route simulation for generating test vectors.The test vectors of the interconnect lines with the same distribution pattern can be designed in the same way,and then all the test vectors of FPGA interconnect lines can be completed.At the end of this essay,the author evaluates the whole test scheme according to the results of simulation and actual test,and puts up a new thought that is used to promote the test scheme.The solution in this paper is for practical engineering,belonging to a special project for FPGA interconnect integrity authentication.It's fast and efficient applying this solution to chip production test.If we want to achieve the test for all interconnect lines in FPGA,just need to configure a chip five times.The scheme in this paper can be parameterized and transplanted.The FPGA through testing for interconnect lines is reliable.