| With the progress of CMOS technology, there is a steady growth in clock frequency and chip capacity. As a result, the power dissipation of deeply scaled digital CMOS design has increased tremendously. On the other hand, low power VLSI designs are crucial in many areas, such as mobile phones. Furthermore, according the 2011 International Technology Roadmap for Semiconductors (ITRS), the trend towards high power consumption is far beyond the power requirement. As a result, power optimization techniques are highly appreciated in nowadays VLSI design.;There are various low power methodologies from system level to layout level. In our research, we are focusing on low power techniques from register transfer level (RTL) to transistor level. Clock gating (CG) is the most widely used technique to reduce dynamic power at RTL. One of the traditional CG styles is XOR-based CG. It compares the inputs and outputs of flip-flops (FFs), and gated the FFs when they are the same. However, this CG is not effective since it does not take the signal activities into account. In this thesis, an activity-driven optimized bus specific clock gating (OBSC) is proposed. It uses fine-grained RTL power models to estimate the dynamic power, and chooses only a subset of FFs to be gated selectively based on their switching activities. During the clock gated period, the gated FFs' outputs are stable. As a result, the combinational logics which are completely dependent on these stable outputs can be power gated so as to save leakage power. Thus, CG and power gating (PG) can be integrated to reduce dynamic and leakage power simultaneously. The sleep signal of our PG is the CG enable signal which is generated during the CG implementation. It does not require an individual power management block to generate as in the case of traditional PG implementation. Moreover, in order to determine if PG leads to leakage power savings, minimum average idle time concept is proposed. Lastly, as a critical part in the integration of CG and PG, data retention logics (DRLs) are required to hold the values of the power gated logics' outputs so that the non power gated blocks which depend on those outputs can function correctly during the power gated period. In this thesis, a low power DRL design is presented.;All the above mentioned techniques have been applied to ISCAS'89 benchmark circuits, and their correctness has been verified successfully. Moreover, the whole experimental process is accomplished automatically by software program, so it is easy to be integrated into current EDA tools. |
