| Advances in silicon processing technology have made CMOS power amplifiers a feasible option for wireless communication applications. Compared to the compound-semiconductor counterparts, CMOS PAs become increasingly attractive due to their lower cost and higher level of integration. The continued scaling of CMOS technology further extends the cut-off frequency of CMOS devices up to several hundred GHz, which makes the realization of high performance millimeter-wave CMOS PA a possibility. On the other hand, due to the low breakdown voltage of scaled CMOS and the lossy silicon substrate, the requirement to simultaneously achieve high output power, high linearity, and a wide power control range makes it very challenging for conventional PAs to maintain good efficiency, especially at back-off power levels.;The first focus of this thesis is the implementation of an outphasing PA with dynamic power control (DPC), which addresses the efficiency-linearity trade-off, especially at power back-off. With DPC, segments of the PA are turned on or off dynamically according to the instantaneous power level. This technique has been experimentally demonstrated with a 2.4 GHz fully-integrated watt-level outphasing class-D PA in 45 nm CMOS. With DPC, average PAE is improved from 12% to 16% at 24.8 dBm average output power, and from 5% to 12% at 20.5 dBm output power.;The second focus addresses the design of high performance PAs in the millimeter-wave regime. Various PA and combiner topologies are explored to optimize output power and efficiency. Specifically, a 45 GHz 2-stage class-B PA in SiGe BiCMOS is implemented which achieved 26% peak PAE at 16.6 dBm CW output power. In addition, a transmission line based zero-degree power combiner topology is proposed and analyzed. Using this combiner, a 45 GHz 16-way combined cascoded class-E PA is designed in a 45 nm SOI CMOS process. Simulation results indicate the feasibility of achieving watt-level output power with high PAE with the proposed topology. |
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