Linear RF CMOS circuit design

This thesis presents techniques to improve the performance of linear integrated circuits (IC) in MOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. Integrated devices used in RF CMOS ICs are discussed, and their characteristics related to CMOS process and the applications are briefly reviewed. Several popular transconductor designs in CMOS are also reviewed. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. Although this thesis discusses CMOS integrated circuits at radio frequencies only, this linearization technique is generally applicable and not limited to CMOS or RF circuits. Several applications are presented. A prototype LNA has been fabricated in a 0.25mum CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulations and measurements that the new PA doubles the maximum output power and reduces the DC power consumption by up to 50%.