| In the last few years we have seen an increased interest in millimeter-wave CMOS circuits and communication systems both in academia and industry. The feasibility of CMOS circuits at 60 GHz, the rising interest in digital video, short range, and other high data rate applications, along with the worldwide availability of unlicensed spectrum around 60 GHz have spurred a wave of research targeting integrated 60 GHz CMOS transceivers as a way to achieving low cost, highly integrated, high bandwidth, high data rate communication systems.;In recent years, a number of 60 GHz CMOS building blocks and integrated receivers have been demonstrated. However, the low supply voltage, thin gate oxide, low breakdown voltage, lossy silicon substrate, and power gain---output power tradeoff of CMOS technology result in the millimeter wave power amplifier being the most difficult block to implement in CMOS. A number of 60 GHz CMOS power amplifiers employing different topologies have been reported to date, however the output power has been relatively low, limiting the amplifiers to short-range applications. It is becoming increasingly important to use more efficient power combining techniques in order to increase the output power capability of power amplifiers in order to enable medium and long-range applications.;This research aims at exploring the challenges facing the design and implementation of 60 GHz power amplifiers in standard 90 nm CMOS processes. The design, modeling, and layout optimization of both passive structures such as transmission lines, capacitors, RF pads as well as active devices operating at 60 GHz are investigated. A low-loss power combining technique taking advantage of millimeter-wave amplifiers topologies is presented. Four power amplifiers are implemented in a standard 90 nm 1V CMOS process. Record performance is reached in terms of 1dB compression and saturation output power. |
