| In this research, 'Input vs Path Matrix Technique' and 'Node vs Input Matrix Technique' techniques for reducing the transistor count in the pull-up and the pull-down array of CMOS circuits are studied. Also, algorithms for minimization of both the pull-up tree and the pull-down tree, based on the above techniques, which results in a reduced number of transistors in the optimized tree in comparison to the original structure of CMOS circuits were proposed. A comparison has been done for area, delay and power of the optimized and unoptimized CMOS structures. Simulations for power and delay have been done in HSPICE [4] for both the minimized and unoptimized CMOS structures. Some of the minimized CMOS structures were multiplexers, adders and gray to binary converters. The minimized CMOS structures have been found to be faster, lower in power dissipation and taking less layout area in comparison to the unoptimized CMOS structures. The above techniques can also be applied to the Pseudo-NMOS and Dynamic CMOS circuits besides the regular CMOS circuits. |
