Design and power optimization techniques of CMOS baseband circuits for wideband wireless applications

The wireless communication market has been experiencing tremendous growth and will continue to do so in the next decade. It leads to a high demand for low-power, low-cost, small form factor devices. The objective of this work is to investigate new circuit techniques to design low-power/low-voltage CMOS analog/mixed-signal baseband circuits (data converters, filters, etc) for various wireless applications such as WCDMA, WLAN, Bluetooth, HomeRF, etc.; Reducing power dissipation associated with high speed sampling and quantization is a major problem in A/D converter (ADC) design. Several power optimization techniques used in pipeline ADCs are first analyzed, then a novel technique named dynamic biasing is proposed. An experimental prototype ADC for WLAN (DSSS)/WCDMA direct conversion receivers was designed and fabricated in a 0.5μm CMOS technology. This technique can also be applied to other receiver/ADC architectures.; A novel technique to improve the intrinsic matching of resistor-string D/A converters (DACs) without trimming or calibration is proposed. This technique is demonstrated in the design of a high-resolution control DAC for 3G (UTMS) transceivers.; Low voltage operation is another important key factor in these portable devices. Based on the study of low voltage circuit design techniques, a modified switched-opamp technique suitable for system-on-chip design is proposed. The major novelty and improvement is that it increases the maximum sampling frequency, and employs a novel input stage. A 1.5V 8-bit 20MS/s pipeline ADC was designed and implemented in a 0.18μm CMOS technology for Bluetooth/WLAN(FHSS)/HomeRF applications.; In modern wideband receivers, the analog filter often consumes a large portion of power. Therefore, the design of low-power high-speed active filters will have a significant contribution to the power savings of the entire receiver. A novel fully-differential active filter architecture is developed. It employs only a single active component (DDA) to implement a second-order Sallen-Key filter. A fifth-order low-pass filter was designed and fabricated in a 0.5μ m CMOS technology. This filter exhibits high speed, high linearity, low noise and low power.