| The demand for wireless devices is increasing, new standards are constantly evolving and the operating frequencies are spreading towards higher spectrums. The stress on lowering the voltage supply, the power consumption, the cost and increasing level of integration are the driving forces behind today's RF microelectronics research.; The goal of this thesis is to show the possibility of standard CMOS technology replacing the traditional technologies in RFIC applications, specifically in the design and implementation of frequency synthesizers for 5GHz WLAN applications. The frequency synthesizer is a key building block of WLAN transceivers. To generate multiple frequencies with the resolution required by 5GHz WLAN standards, a fractional-N frequency synthesizer architecture was successfully implemented in 1.8V 0.18mum CMOS technology. To be able to cover the lower and upper 5GHz bands of both HiperLan and 802.11a standards, a wide tuning range quadrature voltage controlled oscillator (VCO), providing a 4-phase output and operating from 5GHz to 6GHz, was used in the phase lock loop (PLL) design. The 5GHz WLAN standards are targeted since they are the most promising, they have few interferers and large data throughputs.; This thesis presents one of the few frequency synthesizers having a large bandwidth of operation and a small resolution reported to-date for this type of application. Also, the digital components used in this frequency synthesizer, namely the fractional-N divider and prescaler have the lowest power consumption reported to-date. |
