Study On Several Critical Techniques Of CMOS ΣΔ Fractional-n Frequency Synthesizer

Frequency synthesizer is a key block in the wireless transceiver. There exist challenges like small layout area, high performance and low power dissipation in the design. In this dissertation, the design and analysis ofΣΔfractional-n frequency synthesizer for RF applications is conducted, and the principal contributions of this dissertation are described in the following.The dissertation presents a number of system issues and design considerations/tradeoffs that are involved in the design of such a frequency synthesizer from the system point of view. These considerations help to properly select loop parameters and key building blocks, and specify noise and nonlinearity of components used in aΣΔfractional-n frequency synthesizer.A set of behavioral voltage-domain verilogA/verilog models allowing a systematic design ofΣΔfractional-n frequency synthesizer is presented in the dissertation. The approach allows the designer to predict the dynamic or stable characteristic of the closed loop by including nonlinear effects of building blocks in the models. So it helps to a speed-up over transistor simulation and a grasp of the fundamentals at the early stage of the design and optimization design at the system level. Simulation and measured results show that behavioral modeling is effective and flexible.A self-adaptive, self-tuning fractional-n PLL based frequency synthesizer is proposed in the dissertation. A combined tuning technique of digital tuning and analog tuning is introduced to effectively enlarge the frequency tuning range in a low gain of VCO. The self-adaptive loop is used to realize automatic adjustment of the loop bandwidth, which can reduce the settling time and improve the spectral purity. Only a programmable counter is needed for the swallow pulse divider. The proposed architecture is implemented in a Personal Handy-phone System (PHS) transceiver, and measured results show that the synthesizer has a <-119dBc/Hz@1MHz phase noise, a <-70dBc spur and a <100μs settling time. The chip consumes 34mW at 1.8V and occupies 1.5mm×1.7mm.TheΣΔfractional-n frequency synthesizer with adaptive digital tuning techniques is deeply discussed in the dissertation. The proposed one can be independently used as a PLL, and it can also be used as a frequency-lock aid for the conventional PLL. An adaptive control is for fast convergence to a proper control word. The proposed architecture is implemented in an IEEE 802.11a/b/g WLAN transceiver, and measured results show that the synthesizer has a <-115dBc/Hz@1MHz phase noise, a <-90dBc spur, a 2.5GHz-4.1GHz frequency tuning range and a <500μs settling time. The chip consumes 36mW at 1.8V and occupies 1.5mm×1.7mm.A spur reduction technique based on charge-averaging principle is presented in the dissertation. The proposed technique can reduce the spurious tones over 30dBc, so it can easily be implemented in the high performance PLL.A new phase self-calibrated scheme for variable delay buffer (VDB) is proposed in the dissertation. The digitally controlled phase calibration removes the disadvantage of conventional analog calibration circuit whose performance is sensitive to process and temperature variations and aging. It is shown that the proposed scheme works properly, and the VDBs consume a 10mA current at L frequency band, and have a <10o quadrature phase shift range.