| The reduced manufacturing and assembly cost, power savings, and increase in reliability are motivation for the move towards integrating analog and digital systems. As a rule, higher levels of integration require additional process complexity and cost. In addition, the bulk of these systems will remain digital and as transistors dimensions fall, device engineering for maximum digital performance compromises analog transistor performance. Asymmetric metal oxide semiconductor (MOS) devices can be included in standard digital complementary metal oxide semiconductor (CMOS) processes with little additional process complexity and display superior analog performance. One class of asymmetric MOS devices---laterally diffused metal oxide semiconductors (LDMOS)---is commonly employed in submicron processes for high voltage applications. A framework which integrates device engineering, model development, testing, and circuit analysis (the gm/Id method) is employed to evaluate the low power operation of a LDMOS transistor in a representative CMOS process available at San Jose State University. |
