Research And Design On Low-power Analog Baseband Chain In 65nm CMOS

In recent years,with the development of wireless communication technology,mobile communication has entered the daily life of people and greatly improved the quality of our life.In order to increase the mobile communication speed and increase the mobile endurance,it requires to design a higher speed and lower power consumption communication circuit,which puts forward higher requirements for the design of the current radio frequency and analog baseband integrated circuits.In this paper,a low power analog baseband circuit chip is designed for wireless communication transmitter system.The chip circuit functions include amplification and attenuation of gain,suppression of out-of-band signal and cancellation of DC offset signal.According to the function of the circuit,the chip design mainly includes programmable amplifier(PGA),channel selection filter,DC offset cancellation circuit(DCOC).This paper first analyzes the impact and challenges of ICs in deep sub-micron technology,and then introduces the transmitter's direct upconversion architecture and the analog baseband associated with it.According to the requirements of the indicator to determine the analog baseband circuit system scheme.In this paper,the channel selection filter for the fourth-order Chebyshev Gm-C low-pass filter,using two quadratic filter unit cascading way.In order to improve linearity and reduce power consumption,the quadratic filter unit of this paper is composed of transconductance amplifiers with source feedback.At the same time in order to increase the common mode rejection of the circuit,the transconductance amplifier has both common mode feedback and common mode feedforward.To prevent the effects of process,temperature,and supply voltage(PVT)on the cut-off frequency of the filter,the cut-off frequency of the filter can be adjusted via the capacitor array.This programmable gain amplifier is divided into attenuation and amplification stage.Based on the consideration of power consumption,the attenuation level of PGA is realized by the passive resistor R-2R attenuation network.For the realization of the amplifier stage,the PGA based on the source degeneration resistance is selected as the basic structure,and the bandwidth expansion technology is used to improve the programming amplifier bandwidth.To prevent the harm caused by the DC offset,the DC offset cancellation circuit of this paper uses a low-pass negative feedback method.In order to reduce the problem of excessive capacitance on the negative feedback circuit,the Miller effect is used to realize the large capacitance.The output stage of the DC offset circuit is a transconductance amplifier,which is connected to the feedback resistance of the main circuit to cancel the DC offset.This design is completed by TSMC 65nm CMOS process.According to the basic principles and processes of layout design,the layout design of the analog baseband circuit is completed,and all the functions are verified by the post-simulation.Post-simulation results show that the analog baseband consumes 4.1mA at a supply voltage of 1V e,which realizes the goal of low power consumption.The bandwidth is adjustable in three bandwidths of 80MHz,100MHz and 120MHz,the range of gain adjustment is-18?30dB,the gain step is 1dB.According to the post-simulation results of the circuit,the performance meets the design requirements of the system for the analog baseband circuit and can be applied to the broadband low-power wireless communication transmitter.