| After the emergence of iterative decoding in the late 1990's, analog decoding design became a powerful alternative to conventional digital implementation. Our goal is to design and implement an entire analog receiver including an analog decoder and a low power analog Fast Fourier Transform (FFT) input interface. The analog decoder part of the design was recently demonstrated by a doctoral candidate. This project focuses on the design of a novel analog FFT processor. The methodology of the design is based on mutually considering system and circuit levels. We simulated the system considering different circuit issues. We modeled an accurate mathematical input referred mismatch source for the N-FFT. We showed that the higher radix FFT structures like DFT have reduced sensitivity to mismatch and reduced number of current mirrors. Subsequent to our work a 180-nm realization was designed and fabricated in collaboration with another M.Sc. candidate. |
