| Power, linearity and speed are fundamental metrics of ADC. Intuitively, components with larger area have better matching (linearity), but need more current to retain the speed, thus leading to more power. Such tradeoff incurs essential challenges to optimize ADCs that sustain high linearity and speed but consume low power. Successive Approximation Register (SAR) ADC, whose area and power efficiency overwhelms other types of ADC due to its efficient binary searching algorithm. Unsurprisingly, it draws huge attention recently. Owing to its amazing flexibility, it holds a wide range of applications in: (1) industries, automobiles, image sensors and biomedicines within 5 Ms/s, (2) videos and GSM RX/TX/BS (5 Ms/s∼200 Ms/s), (3) UWBs, wirelesses, disk readers at 200 Ms/s∼5 Gs/s, and finally (4) optical communications (above 5 Gs/s), categorized according to the sampling rate.;This thesis exploits several new design techniques/algorithms to optimize the design tradeoff in SAR ADCs. We first present an extensive study on the switching energies and linearity on prior and proposed Capacitive Digital-to-Analog Converters (CDAC), the key functional block in the SAR ADC. Theoretically, our proposed CDACs, namely Split-MSB with LSB set-to-down (w/o or w/ charge recycling), reserve optimal tradeoffs between energies and linearity. For specific applications, Unit capacitor array (UCA) performing the highest DNL and bridged-capacitor array (BWA) with unit bridge capacitor occupying the least area are introduced. Potentially, the latter one consumes the least energy if capacitor mismatches are calibrated out.;First two prototypes fabricated in 0.13-microm CMOS technology demonstrate the energy efficiency on SAR ADCs using Split-MSB with LSB set-to-down (w/o or w/ charge recycling). Even though a process limited MIM unit capacitor of 29.8 fF is used, our ADCs achieve figure of merit (FOMs) of 44.1 fJ/conversion step and 31.8 fJ/conversion step, respectively. Specifically, they output effective number of bits (ENOBs) of 8.9 and 8.8 bits over an Effective Resolution Bandwidth (ERBW) of around 1 MHz, and consume 23.2 microW and 15.6 microW under multiple supplies: analog 1.0 V, reference 1.0 V and digital 0.5 V, when both operate at the sampling frequency of 1.1 Ms/s.;To outline the area and power advantages on BWA with unit bridge capacitor, we introduce calibration CDACs to compensate capacitor mismatch induced errors. However, the introduction of calibration CDAC invokes design complexities with abundant of unknown parameters, thus a systematic consideration is drawn to simplify the design. With an assist of a low-offset comparator using capacitive calibration, the 14-bit ADC based on BWA with 3-sigma process capacitor mismatches achieves a 13.4 ENOB in simulation after calibration. The worst DNL at mid-code transition improves to zero mean and one LSB standard deviation in 100 Monte Carlo runs. When it operates at 1 Ms/s in 1.8-V supply, the fabricated ADC in 0.18-microm CMOS consumes 274-microW power. The FOM at this point is around 25 fJ/conversion step. The main ADC without calibration CDACs occupies the area around 0.12 mm2.;Last, this thesis examines effects on linearity, speed, area and power consumption on stage resolution while pipelining multistage SAR ADCs for high speed and high resolution. Several conclusions are reached with behavior analysis. First, high resolution in the 1st stage improves the linearity and even the speed of the op-amp under certain cases. Second, the open loop gain requirement on the op-amp is independent of the stage resolution and becomes crucial. Third, a medium stage resolution is the best candidate while area and power consumption of all active circuitries are decades of those of unit capacitors in the sub SAR ADC. |
