Research In High-speed Serial Link Circuit Design Technology Based Upon USB2.0

USB2.0 (Universal Serial Bus) has become the interface criterion between PC and peripheral equipment. However, the key circuit-design technology in USB2.0 has only been in control of few corporations abroad, such as Intel, Philips, while keep blank in China. Not only from meeting the market requirement, but also to boost the National design ability in IC field, we are stringent to develop our own USB2.0 interface chip (or IP core).As a typical mixed-signal circuits, USB2.0 interface chip composes analog components inevitably, meanwhile it must process high-speed (480Mbps) serial data signal. Due to well-known difficulties in analog-design procedure and un-compatible with digital manufactural process, this paper brings forward novel design methodology: digital-based analog (DBA) arithmetic, and apply which in kernel modules such as transmitter, DRC and clock-generator circuits (DLL) and so on successfully.The idea in DBA lies in realizing analog, mixed-circuit function utilizing digital method, design most part of circuit with digital arithmetic. As a result, DBA design methodology avoids the difficulty of analog parameter design and process control, increases circuit design precision and stability, while keep rather immune to most noise, shoud be very prospective in mixed-signal design field.In the design of transmitter circuits, this paper presents novel circuit topology which can work both in high-speed mode and full-speed mode, in turn reduce the extra capacitance lies in pins of chip, while simplified the design flow; The receiver circuits in the chip adopts novel optimized topology in order to increase the precision of sample, hold and process; In the design of DRC, we adopts novel 5-times dll-oversampling-based digital algorithm and look-up table skills without complex clock recovery procedure, which increased tolerance of high-speed serial data steam signal against skew and jitter.Based upon TSMC 0.25um mixed-signal process, the chip described in the dissertation has been designed using top-down design flow. Key components in the chip, including transmitter, receiver, and bandgap voltage reference circuits has been taped out (MPW) in ICC, shanghai. The test results revealed that all paraments of transmit and receive function are in accordance with USB2.0 requirements well with proper bandgap reference voltage.Besides, the novel data-process circuit in link layer, 5-phase high-precision clocks in pll and dll circuits, all work well through the corresponding post-simulation results.