High Speed Serial Link Transceiver And Parasite Power Supply On Serial Link

Hi-speed base-band serial link transceivers and parasite powered serial bus are studied in the thesis.The research work including;A hi-speed USB2.0 transceiver is designed in 0.13μm mixed-signal CMOS technology and it get a satisfying results in the physically test;The main performances of parasite powered serial bus 1-WIRE are improved such as the capability of parasite power is increased from 5μA to 1mA,and the data rate is increased from 143kbps to 1Mbps.On the hi-speed base-band serial communication,firstly the typical system architecture of hi-speed serial link transceivers is described,including transmission model of communication cable,principles of equalizer,Phase-Locked-Loop(PLL) based Clock and Data Recovery(CDR)circuits,Phase Detectors and Ring Voltage-Controlled Oscillator.Secondly a USB 2.0 hi-speed transceiver is designed in 0.13μm Mixed-signal CMOS technology.Compared with the conventional USB transceivers,some circuits has been improved to work with the ultra low supply voltage of 1.2V,such as envelope detector,phase detector,loop filter in PLL,and analog continuously adjusting Common-Mode Feedback circuit(CMFB).The transceiver has been fabricated in SMIC in 0.13μm Mixed Signal & RF 1P8M Salicide 1.2/3.3v technology.The transmitter jitter(RMS)is 53ps at the data rate of 480Mbps,and the bit error rate(BER)of receiver is less than 10^-12.The power consumption is 10.8mW when idle,14.4mW when receiving and 42.5mW when transmitting,respectively.The die size is ad-limited to 1.936mm×1.936mm,within which the area of the transceiver was 900μm×700μm.On parasite powered serial bus,two solutions were carried out to overcome the difficulties 1-WIRE met;insufficient low capability of parasite power and data rate. First,an adaptive pull-up circuit in the bus master takes the place of fixed resistance pull-up,such the strength of pull-up can be adapted automatically to the level of the 1-WIRE that the parasite power supply capability is increased from 5μA to 1mA in average,and 10mA of a peak.Furthermore,the proposed bus master was backward compliant with the traditional 1-WIRE slave devices;Second,a package-asychronziation mode takes the place of bit-asynchronization in 1-WIRE,such the efficiency of transmission bandwidth is increased remarkably that the highest data rate is increased from 143kbps to 1 Mbps.The prototype circuit is developed,and it is verified by simulation in TSMC 0.25μm Logic CMOS technology.