Low power 4Gbps CMOS serial transceiver

It is mainly focused on designing a TSMC 0.18um low power, low jitter, and small area CMOS 4Gbps serial link transceiver that is fully compliant to the Fiber Channel standard I/O specification. In order to reduce power dissipation, a digital CDR tracking loop design is selectively implemented by TSMC standard library cells. CMOS multi phase differential PLL and single-ended DLL designs are also selected to minimize the power and area. CMOS samplers and phase interpolator designs are chosen for power and area concerns. To lower output and input jitter, CML serial driver equalizer and receiver equalizer designs are mainly added for complying with the Fiber Channel standard I/O specification and back-plane signal integrity features. The simulated power dissipation for driver and receiver blocks are respectively 35mW and 34mW including power consumption of PLL and DLL.