Optimization tools and techniques for Configurable Digital Signal Processor Synthesis

This dissertation presents the Configurable Digital Signal Processor Synthesis (CPS) System, a hardware synthesis system which produces a library of algorithm-specific digital signal processors (ASDSPs) wherein each processor executes a specific digital signal processing (DSP) algorithm. Each processor contains a small instruction set and implements a particular algorithm. The ASDSPs are used to alleviate bottlenecks in software by replacing computationally intense portions of a high level software description of a DSP application with custom hardware. FPGA logic utilization is maximized during Resource Allocation which identifies the computational primitive or function core and replicates is as many times as possible. A novel multi memory ASDSP architecture allows the CPS system to generate processors that perform multiple memory reads and writes in a single cycle. Since the function cores are pipelined, function core operations are scheduled to optimize the number of clock cycles, and function cores are replicated for parallel execution of the algorithm's computational primitive to innately achieve high performance. Each ASDSP generated by the CPS system is individually implemented onto a commercially available field-programmable gate array (FPGA).;The CPS system produces algorithm-specific DSPs that maximize FPGA logic utilization, reduce the number of memory accesses and reduce execution time. This is accomplished via taking advantage of a novel multi-memory ASDSP architecture that significantly reduces the number of memory accesses; a compilation system that automates the hardware synthesis process; and a library of algorithm-specific digital signal processors. An initial DSP algorithm written in C/C++ is read by the CPS system which translates it into a behavioral description of a digital signal processor written in a HDL. This behavioral level description is then translated into a register-transfer level description that is, in turn, processed by logic synthesis and placed and routed on an FPGA. The best speedup in execution time is 13.57 for the complex magnitude processor. Our execution times include communication time as well as computation time.