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Design And Implementation Of Digital Low-Frequency Time-Code ReceiverBased On FPGA

Posted on:2008-08-28Degree:MasterType:Thesis
Country:ChinaCandidate:G D LiFull Text:PDF
GTID:2178360215489390Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
With the development of the technology, the design of electronic circuit is getting rid of traditional pattern, while using FPGA (Field Programmable Gate Array ) to design electronic circuit is becoming the trend of design. Because using FPGA to design electronic circuit has the advantage of short time and relative less fund, and can make product as electronic circuit to product as CMOS chip.In this paper, a LF (low frequency) time-code receiver which is used in LF time-code service system is designed based on FPGA. The main works and contributions can be summarized as follows:(1)The developing trends of LF time-code receiver is discussed. This paper discusses the base conception and specialty of the software radio, analyze the base three frameworks of the software radio. On the basis of this, discuss the realize method and structure of LF time-code receiver based on software radio.(2)Using the EAD design method. The design of LF time-code receiver is in a hiberarchy way which is to modularize complex circuit from top to bottom. Two main parts of LF time-code receiver are data acquisition and processing module and controlling module. There are many small modules in these two modules. The connection and reality method of these small modules are given. What is more, the paper put forward a kind of method which is data acquisition when one second began to synchronize the output of LF time-code receiver.(3)The hardware design of LF time-code receiver based on FPGA is given. The differential input mode of ADC is designed. The main circuit of LF time-code receiver is expound, such as key, LCD, UART and so on.(4)This paper introduces the design scheme of FIR filter based on FPGA. My research has implemented digital demodulation and looking at the timing reference point of the receiver based and FPGA.(5)A scheme of digital phase shifter is introduced,which is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language).The principle of digital phase shifter is introduced. In addition, flip-latch, frequency divider, automation module and time code operation module are also implemented.
Keywords/Search Tags:digital receiver, LF time-code signal, software radio, FPGA, VHDL, digital phase shifter, FIR, time system equipment
PDF Full Text Request
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