| With shrinking feature sizes, increasing device density, decreasing supply voltages, and increasing clock rates, contemporary digital and mixed-signal designs suffer from the reliability degradation caused by radiation-induced soft errors. Modeling, mitigating, and testing techniques have been the top challenges in the field of soft error research. This dissertation summarizes our contributions to all three aspects: an analysis methodology, four classes of design techniques, and a testing methodology.; We have developed a Soft Error Rate Analysis (SERA) methodology to systematically analyze the impact of soft errors on combinational logic. SERA employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. It achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error.; We also propose four classes of transistor-level soft-error tolerant circuit design techniques: Built-In Soft Error Resilience (BISER), Dual Port Gate (DPG), Dual Sampling Skewed CMOS (DSSC), and Two-Phase Transient-Tolerant circuit style (TPTT). The BISER technique is devised for sequential elements such as latches and flip-flops. It reuses existing on-chip design-for-test resources to improve the reliability of sequential elements, and achieves superior power and area, efficiencies. The DPG technique targets critical sequential and combinational circuits such as latches, voters, and decoders. It employs a novel circuit topology to avoid soft error through active body bias and transient noise attenuation. The DSSC technique is applicable to cycle-based data path design. It combines a novel dual-sampling flip-flop and a skewed CMOS combinational circuit to mitigate the impact of single event transients (SET) with both polarities, and thus provides a cost-effective way to improve the reliability of large combinational logic circuits. The TPTT technique targets latch-based designs where two clock phases are used. It employs a novel transient-tolerant latch style and a noise-tolerant precharge domino to mitigate SETS, while maintaining high performance.; We propose a cost-effective testing scheme for verification of proof-of-concept soft-error tolerant designs. It is based on the observation that crosstalk noise can be intentionally introduced into a dense layout to emulate SETS. It has been implemented on a test chip featuring the TPTT technique. |
