Research And Design Of Robust Latches For Soft Error Tolerance In Integrated Circuits

With the continuous development of integrated circuit manufacturing level, the chip integration is getting higher and higher, the operating frequency is getting faster and faster,the working voltage and the transistor threshold voltage is decreasing, the transistor size is decreasing year by year, so the amount of the critical charge of the chip circuit internal node is also a continuous reduction, resulting in continuous soft circuit error rate.Due to the increasing influence of soft errors on the integrated circuit, a new high-speed and low-power reinforced latch structure is designed for the defects in existing latch circuit structure scheme. This dissertation proposed a novel C-element connection method which greatly reduces the short-circuit power consumption of the latch module;The improvement of output stage C-element allows the reinforcement for the critical charge of its own internal node It also stabilizes the values of output node,so that the output node will avoid staying in high impedance state when the input is attacked, thus raising the ability to resist soft errors for the overall latch.The reliability of the structure is verified by HSPICE in the 22nm prediction technology model,and also compared with several state-of-the-art anti-soft error latch structures. The experimental results demonstrate that the latch designed in this thesis realizes the performance improving for power consumption, delay and anti-soft error ability by sacrificing 25.78% transistor counts. Power consumption and latency were reduced by 43.12%, 46.25% on average, respectively. Power consumption delay product drop of 37.61%?97.50%,68.98% for average value. It is clear that the design has a high reliability, while power consumption and delay and other indicators were also increased significantly.