| The demand for smaller and faster portable equipment has pushed the circuit technology to a dramatic reduction in feature sizes entering the nanometer domain. This resulted in devices that are scaled down in threshold voltage and gate oxide thickness. The consequence is a significant increase in Static Power Dissipation (SPD). SPD in modern CMOS fabrication technologies is a major component of the total power dissipation, which impedes high level of integration and impact battery life in portable equipment.;This work leads to the development and recommendation of optimized circuit topologies and architectures of arithmetic circuits taking into consideration both static and dynamic power dissipation.;Keywords: Arithmetic Circuit, Static Power Dissipation, Adder, Power Gating, Sleep Transistor.;In this thesis, various components of the SPD are examined. Circuit topologies for basic arithmetic components are evaluated for fabrication technologies of 65nm and down to 32nm. Architectures of adder circuits are analyzed and simulation results are presented. Circuit techniques to reduce SPD are also evaluated. |
