New Approaches To Soft Error Mitigation For Digital Circuits

The soft error mitigation for digital circuits is an important part of research of very large scale Integrated circuits (VLSI). With the technology scaling, little critical charge induced by lower operating voltages and process variation contribute to the ever-increasing soft error rate (SER). High-energy particle radiation induced soft errors have become the predominant reliable issues for space and aero applications.In order to address the soft error mitigation issues, several works have been done in this dissertation. The main research contents and innovations in this dissertation are as follows:(1) A dual-interlocked latch applied to soft error tolerance (DIL-SET) is presented. DIL-SET utilizes dual interlocked scheme and C-element at the outputs to mitigate SEU. DIL-SET can also mitigate SET using time-shifted technique. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented DIL-SET is more area efficient, delay and power efficient.(2) Partial hardening techniques are presented, which replace common standard cells with DIL-SET in the netlist. Firstly, random asynchronous reset is used to inject faults. Secondly, soft error vulnerability of each cell is calculated. Thirdly, appropriate strategy is used to replace common standard cells with DIL-SET. Area-first hardening strategy and speed-first hardening strategy is presented with corresponding experimental results.(3) This dissertation proposes a soft-error-tolerant BIST structure: FT-CBILBO. As an evolution of CBILBO, FT-CBILBO reuses scan chain to construct DMR fault-tolerant scheme and reduce the overhead. FT-CBILBO can block soft error to prevent the propagation of soft error. This dissertation also proposes several evolution of FT-CBILBO, such as SET-CBILBO,XOR-CBILBO,TMR-CBILBO.(4) This dissertation proposes two kinds of self-recovery FSMs named as CG-FSM and De-FSM. CG-FSM sets hardware checkpoint at the register transfer level (RTL) and recovers from transient fault quickly using error detecting code. Compared with the traditional rollback recovery, the proposed approach uses gated-clock technique and makes great improvement in area and power. CG-FSM has good real-time built-in self-recovery performance. De-FSM decomposes the original FSM to two sub-FSMs. One sub-FSM can act as the checkpointing of the other sub-FSM, and vice versa. The introduction of decomposition effectively simplifies the FSM, which can reduce the critical path and improve the performance.